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900 mhz ism band analog rf front end adf9010 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 840 mhz to 960 mhz ism bands rx baseband analog low-pass filtering and pga integrated rf tx upconverter integrated integer-n pll and vco integrated tx pa preamplifier differential fully balanced architectures 3.3 v supply low power mode: <1 ma power-down current programmable rx lpf cutoff 330 khz, 880 khz, 1.76 mhz, and bypass rx pga gain settings: 3 db to 24 db in 3 db steps low noise bicmos technology 48-lead, 7 mm 7 mm lfcsp applications 900 mhz rfid readers unlicensed band 900 mhz applications functional block diagram agnd dgnd 4 24-bit input shift register phase frequency detector prescaler p/p + 1 n counter n = bp + a pll dc offset correction dc offset correction tx out p tx out n tx bb ip tx bb in tx bb qp tx bb qn cp ref in s clk s data s le av dd dv dd v p muxout rx cm r counter b counter a counter v cm v cm r set rx in ip rx in in rx bb ip rx bb in rx bb qp rx bb qn rx in qp rx in qn ovf c ext 1 c ext 2 c ext 3 c ext 4 c t ce adf9010 lo out p lo out n quadrature phase splitter charge pump r x v dd v tune 07373-001 figure 1. general description the adf9010 is a fully integrated rf tx modulator and rx analog baseband front end that operates in the frequency range from 840 mhz to 960 mhz. the receive path consists of a fully differential i/q baseband pga, low-pass filter, and general signal conditioning before connecting to an rx adc for baseband conversion. the rx lpf gain ranges from 3 db to 24 db, programmable in 3 db steps. the rx lpf features four programmable modes with cutoff frequencies of 330 khz, 880 khz, and 1.76 mhz, or the filter can be bypassed if necessary. the transmit path consists of a fully integrated differential tx direct i/q upconverter with a high linearity pa driver amplifier. it converts a baseband i/q signal to an rf carrier-based signal between 840 mhz and 960 mhz. the highly linear transmit signal path ensures low output distortion. complete local oscillator (lo) signal generation is integrated on chip, including the integer-n synthesizer and vco, which generate the required i and q signals for transmit i/q upconver- sion. the lo signal is also available at the output to drive an external rf demodulator. control of all the on-chip registers is via a simple 3-wire serial interface. the device operates with a power supply ranging from 3.15 v to 3.45 v and can be powered down when not in use.
adf9010 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 transmit characteristics .............................................................. 3 receive baseband characteristics .............................................. 4 integer-n pll and vco characteristics .................................. 5 write timing characteristics ...................................................... 6 absolute maximum ratings ............................................................ 7 transistor count ........................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 circuit description ......................................................................... 12 rx section .................................................................................... 12 lo section ................................................................................... 12 r counter .................................................................................... 12 a and b counters ....................................................................... 12 tx section .................................................................................... 14 interfacing ................................................................................... 14 latch structure ........................................................................... 15 control latch .............................................................................. 21 tx latch ....................................................................................... 21 rx calibration latch .................................................................. 21 lo latch ...................................................................................... 22 rx latch ....................................................................................... 22 initialization ................................................................................ 22 interfacing ................................................................................... 22 applications information .............................................................. 23 demodulator connection ......................................................... 23 lo and tx output matching .................................................... 24 pcb design guidelines ............................................................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 8/08revision 0: initial version
adf9010 rev. 0 | page 3 of 28 specifications transmit characteristics av dd = dv dd = 3.3 v 5%, agnd = dgnd = gnd = 0 v, t a = 25c, dbm refers to 50 , 1.4 v p-p differential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, unless otherwise noted. table 1. parameter b version 1 unit test conditions/comments min typ max transmit modulator characteristics operating frequency range 840 960 mhz range over which uncompensated sideband suppression < ?30 dbc output power 3 dbm v iq = 1.4 v p-p differential output p1 db 10 dbm carrier feedthrough ?40 dbm sideband suppression ?46 dbc output ip3 24 dbm p out = ?4 dbm per tone, 10 mhz and 12 mhz baseband input frequencies used. noise floor ?158 dbm/hz transmit baseband characteristics input impedance of each pin 4 k typ single-ended frequencies up to 2 mhz input capacitance of each pin 3 pf at 10 mhz input signal level 1.4 v p-p measured differentially at i or q common-mode output level 0.6 v tx baseband 3 db bandwidth 20 mhz power supplies voltage supply 3.15 3.45 v i dd digital i dd 5 6 ma rx baseband 70 80 ma maximum gain settings tx modulator 140 ma full power, baseband inputs biased at 0.5 v lo synthesizer and vco 140 ma + 5 dbm lo power setting selected total i dd 360 410 ma power-down rx v dd 1 ma av dd 1 20 a dv dd 1 20 a logic inputs (serial interface) input high voltage, v inh 1.4 v 1.8 v logic compatible input low voltage, v inl 0.4 v input current, i inh /i inl 1 a input capacitance, c in 5 pf logic outputs (muxout) output high voltage, v oh dv dd ? 0.4 v i ol = 500 a output low voltage, v ol 0.4 v i oh = 500 a 1 operating temperature range for the b version is ?40c to +85c.
adf9010 rev. 0 | page 4 of 28 receive baseband characteristics av dd = dv dd = 3.3 v 5%, agnd = dgnd = gnd = 0 v, t a = 25c, dbm refers to 50 , 1.4 v p-p differential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments min typ max receive baseband pga highest voltage gain 24 db lowest voltage gain 3 db gain control range 18 db programmable using 3-bit interface gain control step 3 db noise spectral density (referred to input) 3.5 nv/hz at maximum pga gain receive baseband filters 3 db cutoff frequency (mode 0) 320 khz after filter calibration gain flatness 0.5 db typical from dc to 90 khz differential group delay 500 s dc to 360 khz 150 s 170 khz to 310 khz attenuation template after filter calibration @ 330 khz offset ?3 db @ 500 khz offset ?8 db @ 1 mhz offset ?28 db 3 db cutoff frequency (mode 1) 880 khz after filter calibration gain flatness 0.5 db dc to 90 khz differential group delay 500 s dc to 360 khz 150 s 170 khz to 310 khz attenuation template after filter calibration @ 880 khz offset ?3 db @ 2 mhz offset ?17 db @ 4 mhz offset ?38 db 3 db cutoff frequency (mode 2) 1.76 mhz after filter calibration gain flatness 0.5 db dc to 90 khz differential group delay 500 s dc to 360 khz 150 s 170 khz to 310 khz attenuation template after filter calibration @ 1.76 mhz offset ?3 db @ 4 mhz offset ?18 db @ 8 mhz offset ?38 db @ 16 mhz offset ?60 db 3 db cutoff frequency (mode 3) 4 mhz after filter calibration gain flatness 0.5 db dc to 90 khz differential group delay 500 s dc to 360 khz @ 2 mhz offset ?0.5 db @ 4 mhz offset ?2 db input impedance of each pin @ 24 db gain 250 @ 3 db gain 4 k input capacitance of each pin 3 pf at 10 mhz input signal level 2 v p-p measured differentially at i or q common-mode output level 1.65 v on rx baseband outputs maximum residual dc 150 mv baseband gain 0 db ? 27 db 1 operating temperature range for the b version is ?40c to +85c.
adf9010 rev. 0 | page 5 of 28 integer-n pll and vco characteristics table 3. parameter b version 1 unit test conditions/comments min typ max vcooperating frequency 3360 3840 mhz lo output characteristics measured at lo output (900 mhz) vco control voltage sensitivity 8 mhz/v 3.6 ghz vco frequency (taking into account divide by 4) harmonic content (second) ?27 dbc harmonic content (third) ?14 dbc frequency pushing (open loop) 1.2 mhz/v frequency pulling (open loop) 10 hz into 2.00 vswr load. lock time 1000 s 10 khz loop bandwidth output power ?4 to +5 dbm lo outputs combined in a 1:1 transformer; programmable in 3 db steps output power variation 3 db noise characteristics measured at lo output (900 mhz) vco phase noise performance 2 @ 100 khz offset ?120 dbc/hz @ 1 mhz offset ?141 dbc/hz @ 10 mhz offset ?154 dbc/hz in-band phase noise 3 , 4 ?96 dbc/hz @ 1 khz offset from carrier normalized in-band phase noise floor 3 , 4 ?220 dbc/hz spurious frequencies at output channel spacing ?70 dbc 900 mhz offset, 1 mhz pfd frequency, 250 khz channel spacing; loop bandwidth = 7.5 khz phase detector phase detector frequency 5 8 mhz maximum allowable prescaler output frequency 6 325 mhz charge pump i cp sink/source with r set = 4.7 k high value 5 ma low value 0.625 ma r set range 2.7 10 k i cp three-state leakage current 0.2 na sink and source current matching 2 % 1.25 v v cp 2.5 v i cp vs. v cp 1.5 % 1.25 v v cp 2.5 v i cp vs. temperature 2 % v cp = 2.0 v pll reference reference clock frequency 10 104 mhz reference clock sensitivity 0.7 pll v dd v p-p reference input capacitance 5 pf ref in input current 100 a 1 operating temperature range for the b version is ?40c to +85c. 2 the noise of the vco is measur ed in open-loop conditions. 3 the phase noise is measured with the eval-adf9010ebz1 evaluation board and the agilent e50 52a spectrum analyz er. the spectrum analyzer provides the ref in for the synthesizer; offset frequency = 1 khz. 4 f refin = 10 mhz; f pfd = 1000 khz; n = 3600; loop bw = 25 khz. 5 guaranteed by design. sample tested to ensure compliance. 6 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value.
adf9010 rev. 0 | page 6 of 28 write timing characteristics av dd = dv dd = 3.3 v 5%; agnd = dgnd = gnd = 0 v; t a = 25c, guaranteed by design, but not production tested. table 4. parameter limit at t min to t max (b version) unit test conditions/comments t 1 10 ns min s data to s clk setup time t 2 10 ns min s data to s clk hold time t 3 25 ns min s clk high duration t 4 25 ns min s clk low duration t 5 10 ns min s clk to s le setup time t 6 20 ns min s le pulse width db2 db1 (control bit c2) db0 (lsb) (control bit c1) db22 db23 (msb) s clck s data s le s le t 3 t 4 t 2 t 6 t 5 t 1 0 7373-002 figure 2. write timing diagram
adf9010 rev. 0 | page 7 of 28 absolute maximum ratings t a = 25c unless otherwise noted. table 5. parameter rating dv dd , rxv dd , av dd to gnd 1 ?0.3 v to +3.9 v rxv dd , av dd to dv dd ?0.3 v to +0.3 v v p to gnd 1 ?0.3 v to +5.5 v digital i/o voltage to gnd 1 ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd 1 ?0.3 v to av dd + 0.3 v charge pump voltage to gnd 1 ?0.3 v to v p to gnd 1 ref in , lo ext p, l o ext n to gnd 1 ?0.3 v to v dd + 0.3 v lo ext p to lo ext n 320 mv operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c lcsp ja thermal impedance 26c/w reflow soldering peak temperature 260c/w time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high-performance rf integrated circuit with an esd rating of <0.5 kv and is esd sensitive. proper precautions should be taken for handling and assembly. transistor count the adf9010 transistor count is 40,454 (cmos) and 994 (bipolar). esd caution 1 gnd = agnd = dgnd = 0 v.
adf9010 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 c t c ext 1 c ext 2 av dd v tune agnd lo ext p lo ext n av dd t xout p t xout n agnd 48 47 46 45 44 43 42 41 40 39 38 37 rx in qn rx in qp rxv dd nc agnd ovf muxout s le s data s clk ce dv dd 1 2 3 4 5 6 7 8 9 10 11 12 rx in ip rx in in rxv dd lo out n lo out p agnd dgnd ref in dv dd v p cp agnd rx bb ip rx bb qp rx bb qn c ext 3 c ext 4 r set av dd tx bb in tx bb ip tx bb qp tx bb qn 35 rx bb in 36 34 33 32 31 30 29 28 27 26 25 top view (not to scale) adf9010 nc = no connect pin 1 indicator 07373-004 figure 3. pin configuration table 6. pin function descriptions pin o. neonic description 1, 2 rx in ip, rx in in input/complementary in-phase input to the receive filter stage. 3, 46 rxv dd receiver filter power supply. this voltage ranges from 3.15 v to 3.45 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. rxv dd must be the same value as av dd and dv dd . 4, 5 lo out n, lo out p buffered local oscillator output. these outputs ar e used to provide the lo for the external rf demodulator. these require an rf choke to av dd and a dc bypass capacitor before connection to a demodulator. 6, 12, 18, 24, 44 agnd analog ground. this is the ground return path of analog circuitry. 7 dgnd digital ground. 8 ref in pll reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k (see figure 13 ). this input can be driven from a ttl or cmos crystal oscillator, or it should be ac-coupled. 9, 37 dv dd digital power supply. this voltage ranges from 3.15 v to 3.45 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 10 v p this pin supplies the voltage to the charge pump. if the internal vco is used, it should equal av dd and dv dd . if an external vco is used, the voltage can be av dd < v p < 5.5 v. 11 cp charge pump output. when enabled, this pin provides i cp to the external loop filter, which in turn drives the external vco. 13 c t a capacitor connected to this pin is used to roll o ff noise from the vco. it should be decoupled to agnd with a value of 10 nf. the output voltage on this part is proportional to temperature. at ambient temperature, the voltage is 2.0 v. 14 c ext 1 a capacitor connected to this pin is used to roll o ff noise from the vco. it should be decoupled to agnd with a value of 10 nf. 15 c ext 2 a capacitor connected to this pin is used to roll o ff noise from the vco. it should be decoupled to agnd with a value of 10 nf. 16, 21, 29 av dd analog power supply. this voltage ranges from 3. 15 v to 3.45 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd .
adf9010 rev. 0 | page 9 of 28 pin no. mnemonic description 17 v tune control input to the vco. this input determines th e vco frequency and is derived from filtering the cp output. 19, 20 lo ext p, l o ext n single-ended external vco input of 50 . this is used if the adf9010 utilizes an optional external vco. these pins are internally dc-biased and must be ac-coupled. ac-couple lo ext n to ground with 100 pf and ac-couple the vco signal with 100 pf through lo ext p. 22, 23 tx out p, t x out n buffered tx output. these pins contain the tx output signal, which can be combined in a balun for best results. 25, 26 tx bb qn, tx bb qp baseband quadrature phase input/compleme ntary input to the transmit modulator. 27, 28 tx bb ip, tx bb in baseband in-phase input/compleme ntary to the transmit modulator. 30 r set connecting a resistor between this pin and agnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is i cpmax = 25.5/ r set where: r set is 5.1 k. i cpmax is 5 ma. 31 c ext 4 a capacitor connected to this pin is used to roll off noise from the vco. it should be decoupled to agnd with a value of 10 nf. 32 c ext 3 a capacitor connected to this pin is used to roll off noise from the vco. it should be decoupled to agnd with a value of 10 nf. 33, 34 rx bb qn, rx bb qp output/complementary filtered quadrature signals from the receive filter stage. the filtered output is passed to the baseband mxfe chip. 35, 36 rx bb ip, rx bb in output/complementary filtered in-phase from the receive filter stage. the filtered output is passed to the baseband mxfe chip. 38 ce chip enable. a logic 0 on this pin powers down the device. a logic 1 on this pin enables the device depending on the status of the power-down bits. 39 s clk serial clock input. this serial clock is used to cloc k in the serial data to the registers. the data is latched into the 24-bit sh ift register on the s clk rising edge. this is a high impedance cmos input. 40 s data serial data input. the serial data is loaded msb fi rst with the two lsbs being the control bits. this is a high impedance cmos input. 41 s le load enable, cmos input. when le goes high, the data stored in the shift register is loaded into one of the four latches; the latch uses the control bits. 42 muxout this multiplexer output allows eith er the pll lock detect, the scaled vco frequency, or the scaled pll reference frequency to be accessed externally. 43 ovf a rising edge on this pin drops the gain of the rx path by 6 db. this is used to rapidly drop the gain if the adc detects an overload. 45 nc no connect. 47, 48 rx in qp, rx in qn input/complementary quadrature input to the receive filter stage.
adf9010 rev. 0 | page 10 of 28 typical performance characteristics ? 40 ?60 ?80 ?100 ?120 ?140 ?160 1k 100m 10k phase noise (dbc/hz) 100k 1m 10m frequency (hz) 07373-013 900mhz lo 10mhz ref in 1mhz pfd integrated phase error: 0.75 rms figure 4. lo phase noise (900 mhz, including open-loop vco noise) 10 9 8 7 6 5 4 3 2 1 0 840 850 880 910 07373-105 tx output power (dbm) lo frequency (mhz) 860 890 920 870 900 930 940 950 960 ?40c 3.15v p out ?40c 3.3v p out ?40c 3.45v p out +25c 3.15v p out +25c 3.3v p out +25c 3.45v p out +85c 3.15v p out +85c 3.3v p out +85c 3.45v p out figure 5. single sideband tx power ou tput (dbm) vs. lo frequency (hz) with supply and temperature variations; outputs combined in 50:100 balun 20 15 10 5 0 ?5 ?10 ?15 ?10 ?5 0 10 20 07373-106 p out (dbm) p in (dbm) 51 5 ?40c 3.15v p out ?40c 3.3v p out ?40c 3.45v p out +25c 3.15v p out +25c 3.3v p out +25c 3.45v p out +85c 3.15v p out +85c 3.3v p out +85c 3.45v p out ideal figure 6. power output vs. base band input power with supply and temperature variations 28 27 26 25 24 23 22 21 20 19 18 840 850 880 910 07373-107 oip3 (dbm) lo frequency (mhz) 860 890 920 870 900 930 940 950 960 ?40c 3.15v oip3 ?40c 3.3v oip3 ?40c 3.45v oip3 +85c 3.15v oip3 +85c 3.3v oip3 +85c 3.45v oip3 +25c 3.15v oip3 +25c 3.3v oip3 +25c 3.45v oip3 figure 7. output ip3 (dbm) vs. lo frequency (hz), with supply and temperature variations; two-tone test (10 mhz and 12 mhz baseband input frequencies) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 07373-108 sideband supression (dbc) lo frequency (mhz) ?40c 3.15v sbs ?40c 3.3v sbs ?40c 3.45v sbs +85c 3.15v sbs +85c 3.3v sbs +85c 3.45v sbs +25c 3.15v sbs +25c 3.3v sbs +25c 3.45v sbs 840 850 880 910 860 890 920 870 900 930 940 950 960 figure 8. unwanted sideband suppressi on (dbc) vs. lo frequency (hz) with supply and temperat ure variations 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0.2 1.0 1.8 2.6 3.4 07373-109 power (dbc) differential input voltage (v) 3.0 0.6 1.4 2.2 25c 3.3v p out (dbm) 25c 3.3v sbs (dbc) 25c 3.3v loft (dbc) 25c 3.3v hd2 (dbm) 25c 3.3v hd3 (dbm) figure 9. second- and third-order dist ortion, sideband suppression (dbc), carrier feedthrough (dbm) and sbs p out vs. baseband differential input level; lo frequency = 900 mhz
adf9010 rev. 0 | page 11 of 28 9 8 7 6 5 4 3 2 1 0 1 100 tx output power (dbm) 10 input frequency (mhz) 07373-110 ?40c 3.15v p out ?40c 3.3v p out ?40c 3.45v p out +85c 3.15v p out +85c 3.3v p out +85c 3.45v p out +25c 3.15v p out +25c 3.3v p out +25c 3.45v p out figure 10. single sideband power vs . baseband input frequency, with supply and temperature variations; maximum gain setting selected; lo frequency = 900 mhz 20 0 ?20 ?40 ?60 ?80 ?100 10k 10m power (db) 100k 1m frequency (hz) 07373-111 fc 330khz fc 1mhz fc 2mhz bypass figure 11. rx filter performance, power vs. input frequency
adf9010 rev. 0 | page 12 of 28 circuit description rx section dc offset correction rx bb ip rx bb in rx in ip rx in in pga setting ovf 07373-005 figure 12. rx filter the rx section of the adf9010 features programmable base- band low-pass filters. these are used to amplify the desired rx signal from the demodulator while removing the unwanted portion to ensure no antialiasing occurs in the rx adc. these filters have a programmable gain stage, allowing gain to be selected from 3 db to 24 db in steps of 3 db. the bandwidth of these filters is also programmable, allowing 3 db cutoff fre- quencies of 330 khz, 880 khz, and 1.76 mhz, along with a bypass mode. the filters utilize a fourth-order bessel transfer function (see the specifications section for more information). if desired, the filter stage can be bypassed. additionally, a rising edge on the ovf pin reduces the gain of the rx amplifiers by 6 db. this is to correct a potential overflow of the input to the adc. updating the rx calibration latch with the calibration bit enabled calibrates the filter to remove any dc offset. the 3 db cutoff frequency (f c ) of the filters is calibrated also. lo section lo reference input section the lo input stage is shown in figure 13 . sw1 and sw2 are normally closed switches; sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 0 7373-006 to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control buffer figure 13. reference input stage r counter the 14-bit r counter allows the input clock frequency to be divided down to produce the input clock to the phase frequency detector (pfd). division ratios from 1 to 8191 are allowed. a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide range of division ratios in the pll feedback counter. the counters are specified to work when the prescaler output is 300 mhz or less. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler (see figure 14 ), make it possible to generate large divider ratios. the equation for n is as follows: n = bp + a where: n is the overall divider ratio of the signal from the external rf input. p is the preset modulus of the dual-modulus prescaler. b is the preset divide ratio of the binary 13-bit counter (3 to 8191). a is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). load load from rf input stage prescaler p/p + 1 13-bit b counter 6-bit a counter to pfd n divider modulus control n=bp+a 07373-007 figure 14. a and b counters prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the a and b cmos counters. the prescaler is programmable. the prescaler can be set in software to 8/9, 16/17, or 32/33. for the adf9010, however, the 16/17 and 32/33 settings should be used. it is based on a synchronous 4/5 core. a minimum divide ratio is possible for fully contiguous output frequencies. this minimum is deter- mined by p, the prescaler value, and is given by (p 2 ? p).
adf9010 rev. 0 | page 13 of 28 pfd and charge pump the phase frequency detector (pfd) takes inputs from the r counter and n counter ( n = bp + a ) and produces an output proportional to the phase and frequency difference between them (see figure 15 ). 07373-008 delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 rdivider ndivider cp output r divider n divider cp cpgnd v p figure 15. pfd simplified schematic and timing (in lock) muxout the output multiplexer on the adf9010 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the control latch. the full truth table is shown in figure 22 . figure 16 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital and analog. digital lock detect is active high. if the ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. with the ldp set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. it stays set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. when a lock has been detected, th is output is high with narrow low-going pulses. r counter output n counter output digital lock detect dgnd control mux muxout dv dd analog lock detect sdout 07373-114 figure 16. muxout circuit voltage-controlled oscillator (vco) the vco core in the adf9010 uses 16 overlapping bands, as shown in figure 17 , to allow a wide frequency range to be covered with a low vco sensitivity (k v ) and to result in good phase noise and spurious performance. the vco operates at 4 the lo frequency, providing an output range of 840 mhz to 960 mhz. the correct band is chosen automatically by the band select logic at power-up or whenever the lo latch is updated. during band select, which takes five pfd cycles, the vco v tune is disconnected from the output of the loop filter and connected to an internal reference voltage. 3.5 3.0 2.5 2. 1.5 1.0 0.5 0 750 800 850 series 1 900 950 1000 07373-020 v tune (v) frequency (hz) figure 17. vco bands the r counter output is used as the clock for the band select logic and should not exceed 1 mhz. a programmable divider is pro- vided at the r counter input to allow division by 1, 2, 4, or 8 and is controlled by bit bsc1 and bit bsc2 in the tx latch. where the required pfd frequency exceeds 1 mhz, the divide ratio should be set to allow enough time to select the correct band. after the band is selected, normal pll action resumes. the nominal value of k v is 32 mhz/v or 8 mhz/v, taking into account the divide by 4. the output from the vco is divided by 4 for the lo inputs to the mixers, and for the lo output drive to the demodulator.
adf9010 rev. 0 | page 14 of 28 lo output mixers the lo out p and lo out n pins are connected to the collectors of an npn differential pair driven by buffered outputs from the vco, as shown in figure 18 . to allow optimal power dissipation vs. the output power requirements, the tail current of the diffe- rential pair is programmable via bit tp1 and bit tp2 in the control latch. the four current levels that can be set are: 6 ma, 8.5 ma, 11.5 ma, and 17.5 ma. these levels give output power levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, respectively, if both outputs are combined in a 1 + 1:1 transformer or a 180 microstrip coupler. the adf9010 has two double-balanced mixers, one for the in-phase channel (i channel) and one for the quadrature channel (q channel). both mixe rs are based on the gilbert cell design of four cross-connected transistors. tx output the tx out p and tx out n pins of the adf9010 are connected to the collectors of four npn differential pairs driven by the baseband signals, as shown in figure 20 . to allow the user optimal power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via bit tp1 and bit tp2 in the control latch. two levels can be set; these levels give output power levels of ?3 dbm and, +3 dbm, respectively, using a 50 resistor to v dd and ac coupling into a 50 load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler. this buffer can be powered off if desired. if the outputs are used individually, the optimum output stage consists of a shunt inductor to v dd . another feature of the adf9010 is that the supply current to the rf output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mute tx until lock detect (f4) bit in the control latch. vco lo out plo out n buffer/ divide by 4 07373-010 another feature of the adf9010 is that the supply current to the tx output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mute lo until lock detect bit (f5) in the control latch. tx out p tx out n lo qp lo qn lo ip lo in ip in qp qn 07373-012 figure 18. lo output section tx section figure 20. tx section tx out p lo ext p lo ext n lo out p lo out n tx out n tx bb qp tx bb qn tx bb ip tx bb in 4 quad phase splitter vco int/ ext 07373-011 interfacing input shift register the digital section of the adf9010 includes a 24-bit input shift register. data is clocked into the 24-bit shift register on each rising edge of s clk . the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of s le . the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in figure 21 . the truth table for bit c3, bit c2, and bit c1 is shown in table 7 . it displays a summary of how the latches are programmed. note that some bits are used for factory testing and should not be programmed by the user. figure 19. tx section tx baseband inputs differential in-phase (i) and qu adrature baseband (q) inputs are high impedance inputs that must be dc-biased to approx- imately 500 mv dc and e driven from a low impedance source. nominal characterized ac signal swing is 700 mv p-p on each pin. this results in a differential drive of 1.4 v p-p with a 500 mv dc bias. table 7. truth table control bits data latch c3 c2 c1 x 0 0 control latch 0 0 1 tx latch 1 0 1 rx calibration x 1 0 lo latch x 1 1 rx filter
adf9010 rev. 0 | page 15 of 28 latch structure figure 21 shows the three on-chip latches for the adf9010. the two lsbs determine which latch is programmed. g2 g3 bw2 t1 t15 t16 t7 t8 t12 t13 t14 hp hpf boost t10 t11 t6 t5 t4 t2 t3 rx filter gain steps g1 t9 rx filter bandwidth bw1 test modes db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) res res f1 m1m2 f2 pd4 res cpi1 cpi2 pd1 pd2 pd3 m3 control bits pd polarity pd pll charge pump current muxout tp1 tp2 db21 p2 p1 f5 db22 db23 counter reset cp three- state f3 f4 control latch tx latch mute lo until ld mute tx until ld lo output power tx output power pd tx pd vco pd rx reserved cpi3 reserved c2 (1) c2 (0) a1a2a3a4a5b1b2b3b4b5b6b7b8b9 b10 b11 b12 b13 5-bit a counter 13-bit b counter prescaler cp gain g1 p2 p1 n div mux m1 r2r3r4r5r6r7r8r9 r10 r11 r12 r13 r1 bsc1 bsc2 t1t2 t3 control bits 13-bit reference counter p2 p1 band select clock p3 r13 bsc1 bsc2 t1t2 t3 p2 p1 p3 tx mod lo phase select tx mod lo phase select lo phase select band select clock lo phase select c3 (0) c2 (0) c1 (1) rc2 rc3 rc4 rc5 rc6 hp2 hp1 hp3 hp4 hp5 hp6 rc1 rx calibration divider rx calibration lo latch rx latch high-pass filter boost timeout counter rx filter cal db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 (1)c2 (0)c1 (1) db2 db1 db0 db21 db22 db23 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 db2 db1 db0 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 db2 db1 db0 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 control bits control bits c2 (1) c1 (1) control bits 07373-014 figure 21. latch summary
adf9010 rev. 0 | page 16 of 28 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) res res f1 m1m2 f2 pd4 res cpi1 cpi2 pd1 pd2 pd3 m3 control bits pd polarity pd pll charge pump current muxout tp1 tp2 db21 p2 p1 f5 db22 db23 counter reset cp three- state f3 f4 mute lo until ld mute tx until ld lo output power tx output power pd tx pd vco pd rx reserved cpi3 reserved i cp (ma) cpi3 cpi2 cpi1 2.7k ? 4.7k ? 10k? 0001 . 2 50 . 6 30 . 3 1 0012 . 5 01 . 2 50 . 6 3 0103 . 7 51 . 8 70 . 9 4 0115 . 0 02 . 5 01 . 2 5 1006 . 2 53 . 1 31 . 5 6 1017 . 5 03 . 7 51 . 8 7 1108 . 7 54 . 3 82 . 1 9 1 1 1 10.0 5.00 2.50 m3 m2 m1 output 0 0 0 three-state output 0 0 1 digital lock detect (active high) 0 1 0 n divider output 011d v dd 1 0 0 r divider output 1 0 1 n-channel open-drain lock detect 1 1 0 serial data output 111d g n d p2 p1 lo output power (combined) 0 0 ?4 dbm 0 1 ?1 dbm 10+ 2 d b m 11+ 5 d b m tp2 tp1 tx output power 00 fully on 01 ?6db 10 ?6db 11 mute pd3 power down pll 0disabled 1 enabled pd2 power down vco 0disabled 1 enabled pd1 power down tx 0disabled 1 enabled f3 charge pump output 0normal 1 three-state f2 phase detector polarity 0negative 1 positive f1 counter operation 0normal 1 counters held in reset f4 mute tx until lock detect 0 disabled 1 enabled f5 mute lo until lock detect 0 disabled 1 enabled pd4 power down rx 0 disabled 1 enabled this bit is reserved for factory testing and should be set to 0 these bits are reserved and should be set to 0, 1 07373-015 figure 22. control latch
adf9010 rev. 0 | page 17 of 28 r2 r3 r4r5r6r7r8r9 r10 r11 r12 r13 r1 bsc1 bsc2 t1t2 t3 control bits 13-bit reference counter p2 p1 band select clock p3 tx mod lo phase select lo phase select x = don?t care c3 (0) c2 (0) c1 (1) db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db21 db22 db23 bsc2 bsc1 band select clock divider 0 0 not allowed 0 1 not allowed 1 0 not allowed 118 these bits are reserved and should be set to 1,1 r13 r12 r11 r3 r2 r1 divide ratio 0 0 0 .......... .......... 0011 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 t3 t2 t1 output 0 0 0 normal quadrature 0 0 1 i to both 0 1 0 q to both 0 1 1 external lo, quadrature 1 x x all off p3 p2 p1 output 000i o u t 001q o u t 010i b o u t 011q b o u t 1 0 0 external i 1 0 1 external q 1 1 0 external i to pll, out off 1 1 1 all off 07373-016 figure 23. tx latch
adf9010 rev. 0 | page 18 of 28 r13 bsc1 bsc2 t1t2 t3 p2 p1 p3 band select clock lo phase select rc2 rc3 rc4 rc5 rc6 hp2 hp1 hp3 hp4 hp5 hp6 rc1 rx calibration divider high-pass filter boost timeout counter rx filter cal c3 (1) c2 (0) c1 (1) db2 db1 db0 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 control bits t3 t2 t1 output 0 0 0 normalquadrature 0 0 1 i to both 0 1 0 q to both 0 1 1 external lo, quadrature 1 x x all off p3 p2 p1 output 000i o u t 001q o u t 010i b o u t 011q b o u t 1 x x all off rc6 .......... rc2 rc1 cal counter divide ratio 0 .......... 0 0 0 0 .......... 0 1 1 0 .......... 1 0 2 0 .......... 1 1 3 . .......... . . . . .......... . . . . .......... . . . 1 .......... 0 0 60 1 .......... 0 1 61 1 .......... 1 0 62 1 .......... 1 1 63 timeout counter cycles hp6 .......... hp2 hp1 0 .......... 0 0 0 0 .......... 0 1 1 0 .......... 1 0 2 0 .......... 1 1 3 . .......... . . . . .......... . . . . .......... . . . 1 .......... 0 0 60 1 .......... 0 1 61 1 .......... 1 0 62 1 .......... 1 1 63 f5 rx filter f c calibration 0d i s a b l e d 1 enabled bsc2 bsc1 band select clock divider 0 0 not allowed 0 1 not allowed 1 0 not allowed 118 these bits are reserved and should be set to 1,1 x = don?t care 07373-017 tx mod lo phase select figure 24. rx calibration latch
adf9010 rev. 0 | page 19 of 28 c2 (1) c2 (0) a1 a2 a3a4a5 b1 b2b3b4b5b6b7b8b9 b10 b11 b12 b13 5-bit a counter 13-bit b counter prescaler cp gain g1 p2 p1 n div mux m1 db2 db1 db0 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 control bits x = don?t care cp gain operation 0 use the programmed charge pump current setting from control register 1 use the maximum charge pump current setting b12 b12 b11 b3 b2 b1 b counter divide ratio 0 0 0 .......... 0 0 0 not allowed 0 0 0 .......... 0 0 1 not allowed 0 0 0 .......... 0 1 0 not allowed 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 a5 .......... a2 a1 a counter divide ratio 0 .......... 0 0 0 0 .......... 0 1 1 0 .......... 1 0 2 0 .......... 1 1 3 . .......... . . . . .......... . . . . .......... . . . 1 .......... 0 0 28 1 .......... 0 1 29 1 .......... 1 0 30 1 .......... 1 1 31 n = bp + a, p is the prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ) at the output, n min is (p 2 ? p). p2 p1 prescaler value 008 / 9 011 6 / 1 7 103 2 / 3 3 113 2 / 3 3 n div mux operation 0 vco feedback to n divider. 1 mux feedback to n divider. 0 7373-018 figure 25. lo latch
adf9010 rev. 0 | page 20 of 28 g2g3 bw2 t1 t15 t16 t7 t8 t12 t13 t14 hp hpf boost t10 t11 t6 t5 t4 t2 t3 rx filter gain steps g1 t9 rx filter bandwidth bw1 test modes db2 db1 db0 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db21 db22 db23 c2 (1) c1 (1) control bits 07373-019 g3 g2 g1 filter gain 0003db 0016db 0109db 0 1 1 12db 1 0 0 15db 1 0 1 18db 1 1 0 21db 1 1 1 24db hp hpf boost 0 disabled 1 enabled bw2 bw1 rx filter bandwidth 00 l o w 01 1 m h z 10 2 m h z 1 1 bypassed these bits are used for factory testing and should not be programmed by the user. they should be set to 0. figure 26. rx latch
adf9010 rev. 0 | page 21 of 28 control latch with (c2, c1) = (0, 0), the control latch is programmed. figure 22 shows the input data format for programming the control latch. power-down programming a 1 to pd4, pd3, pd2, pd1 powers down the circuitry for the rx filters, pll, vco, and tx sections, respectively. programming a 0 enables normal operation for each section. tx output power bit tp1 and bit tp2 set the output power level of the vco. see the truth table in figure 22 . charge pump current bit cpi3, bit cpi2, and bit cpi1 determine current setting 2. see the truth table in figure 22 . lo output power bit p1 and bit p2 set the output power level of the lo. see the truth table in figure 22 . mute lo until lock detect bit f5 is the mute until lock detect bit. this function, when enabled, ensures that the lo outputs are not switched on until the pll is locked. mute tx until lock detect bit f4 is the mute tx until lock detect bit. this function, when enabled, ensures that the tx outputs are not switched on until the pll is locked. charge pump three-state bit f3 puts the charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. phase detector polarity bit f2 sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active noninverting filter. it can also be set to 0. this is required if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, and m1. see the truth table in figure 22 . counter reset bit f1 is the counter reset bit for the pll of the adf9010. when this bit is set to 1, the r, a, and b counters are held in reset. for normal operation, this bit should be 0. reserved bits db3 and db2 are spare bits that are reserved. they should be programmed to 0 and 1, respectively. tx latch with (c3, c2, c1) = (0, 0, 1), the tx latch is programmed. figure 23 shows the input data format for programming the tx latch. lo phase select bit p3, bit p2, and bit p1 set the phase of the lo output to the demodulator. this enables the user to select the phase delay of the rx lo signal to the demodulator in 90 steps. see the truth table in figure 23 . the rx lo output can be disabled if desired. tx modulation lo phase select bit t3, bit t2, and bit t1 set the input modulation of the vco. normal quadrature to each mixer can be replaced by choosing one lo phase to both mixers if desired. the normal (i) or quadrature (q) phase can be chosen. see the truth table in figure 23 . band select clock bits bsc2 and bit bsc1 set a divider for the band select logic clock input. the recommended setting is 1, 1, which programs a value of 8 to the divider. no other setting is allowed. reference counter r13 to r1 set the counter divide ratio. the divide range is 1 (00 001) to 8191 (111 111). rx calibration latch with (c3, c2, c1) = (1, 0, 1), the rx calibration latch is programmed. figure 24 shows the input data format for programming the rx calibration latch. lo phase select bit p3, bit p2, and bit p1 set the phase of the lo output to the demodulator. this enables the user to select the phase delay of the rx lo signal to the demodulator in 90 steps. see the truth table in figure 24 . the rx lo output can be disabled if desired. tx modulation lo phase select bit t3, bit t2, and bit t1 set the input modulation of the vco. normal quadrature to each mixer can be replaced by choosing one lo phase to both mixers if desired. the normal (i) or quad- rature (q) phase can be chosen. see the truth table in figure 24 . band select clock bit bsc2 and bit bsc1 set a divider for the band select logic clock input. the recommended setting is 1, 1, which programs a value of 8 to the divider. no other setting is allowed. rx filter calibration setting bit r13 high performs a calibration of the rx filters cutoff frequency, f c . setting this bit to 0 ensures the filter cutoff frequency calibration sequence is not initiated if this latch is programmed.
adf9010 rev. 0 | page 22 of 28 rx calibration divider bit rc6 to bit rc1 program a 6-bit divider, which outputs a divided ref in signal to assist calibration of the cutoff frequency, f c , of the rx filters. the calibration circuit uses this divideddown pll reference frequency to ensure an accurate cutoff frequency in the rx filter. the divider value should be chosen to ensure that the frequency of the divided down signal is exactly 2 mhz, that is, if a 32 mhz crystal is used as the pll ref in frequency, then a value of 16 should be programmed to the counter to ensure accurate calibration. high-pass filter boost timeout counter in most applications of the adf9010, a high-pass filter is placed between the demodulator outputs and the adf9010 rx inputs. the capacitors used in these filters may require a long charge up time, and to address this, a filter boost function exists that charges up the capacitor to ~1.6 v. the duration for this boost is set by the product of the period of the rx calibration signal, (ref in divided by the rx calibration divider) and the 6-bit value programmed to these registers. this value can be as large as 63. programming a value of 000000 leads to the calibration time being manually set by the hpf boost in the rx latch. it becomes necessary in such cases to program this bit to 0 for normal rx operation. lo latch program the lo latch with (c2, c1) = (1, 0). figure 25 shows the input data format for programming the lo latch. prescaler bit p2 and bit p1 in the lo latch set the prescaler values. cp gain setting g1 to 0 chooses the programmed charge pump current setting from the control latch. setting this bit to 1 chooses the maximum possible setting. n div mux setting m1 to 0 feeds the vco signals back to the n divider. setting this bit to 1 allows the mux signal to be fed back instead. b counter latch bit b13 to bit b1 program the b counter. the divide range is 3 (00 0011) to 8191 (11 111). a counter latch bit a5 to bit a1 program the 5-bit a counter. the divide range is 0 (00000) to 31 (11111). rx latch program the rx latch with (c2, c1) = (1, 1). figure 26 shows the input data format for programming the lo latch. high-pass filter boost this function is enabled by setting the hp bit to 1. a 0 disables this function. this is used to reduce settling time on the high- pass filter from the rx demodulator. this is usually used in conjunction with the high-pass filter boost counter (see the rx calibration latch section). rx filter bandwidth the rx filter bandwidth is programmable and is controlled by bit bw2 and bit bw1. see the truth table in figure 26 . rx filter gain steps bit g3 to bit g1 set the gain of the rx filters. the gain can vary from 3 db to 24 db in 3 db steps. see the truth table in figure 26 . initialization the correct initialization sequence for the adf9010 is as follows: 1. power-down all blocks: tx, rx, pll, and vco. set the tx output power off control latch to (1, 1). set the lo phase select off (p1, p2, p3) in tx latch to (1, 1, 1). 2. program the r1 latch with the desired r counter and tx values. 3. program r5 with rx calibration data for frequency calibration and high-pass filter boost. 4. program r0 to power up all lo and tx/rx blocks. 5. program r2 to encode correct lo frequency. 6. program r3 to power up rx filter. interfacing the adf9010 has a simple spi?-compatible interface for writing to the device. s clk , s data , and s le control the data transfer. see figure 2 for the timing diagram. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 s. this is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.
adf9010 rev. 0 | page 23 of 28 applications information agnd dgnd 24-bit input shift register phase frequency detector prescaler p/p + 1 n counter n = bp + a pll dc offset correction dc offset correction tx out p tx out n tx bb ip tx bb in tx bb qp tx bb qn cp ref in s clk s data s le av dd dv dd v p muxout r counter b counter a counter v cm r set rx in ip rx in in rx bb ip rx bb in rx bb qp rx bb qn rx in qp rx in qn ovf c ext 1 c ext 2 c ext 3 c ext 4 c t ce lo out p lo out n charge pump v cm v tune 07373-003 pa module antenna switch module mxfe sha sha adc agc digital control dac dac 24-bit input shift register clk data le en rx baseband tx baseband balun balun aux dac aux dac aux dac adf9010 r x v dd figure 27. applications diagram the diagram in figure 27 shows the adf9010 in an rfid appli- cation. the demodulator is driven by the lo out x pins of the adf9010. this demodulator produces quadrature baseband signals that are gained up in the adf9010 rx filters. these filtered analog baseband signals are then digitized by the adc on a mixed signal front-end (mxfe) part. the digital signals are then processed by dsp. on the transmit side, the mxfe generates quadrature analog baseband signals, which are upconverted to rf using the inte- grated pll and vco. the modulated rf signals are combined using a balun and gained up to 30 dbm by a power amplifier. demodulator connection to receive the back-scattered signals from an rfid tag, the adf9010 needs to be used with a high dynamic range demodulator, such as the adl5382 that is suitable for rfid applications. some extra filtration is provided by the optional shunt capacitors and series inductors. due to the large self- blocker, a 100 nf capacitor removes the dc generated by the self-blocker inherent to rfid systems. this system is used on the eval-adf9010ebz1 evaluation board. demod adl5382 ihi ilo adf9010 r x in ip r x in in 0 ? 0 ? 100nf 100nf 47pf 1.2nf 07373-021 figure 28. adl5382 to adf9010 rx interface
adf9010 rev. 0 | page 24 of 28 lo and tx output matching the lo and tx output stages are each connected to the collectors of an npn differential pair driven by buffered outputs from the vco or mixer outputs, respectively. the recommended matching for each of these circuits consists of a 7.5 nh shunt inductor to v dd , a 100 pf series capacitor, and in the case of the tx output a 50:100 balun to combine the tx outputs. the anaren bd0810j50100a00 is ideally suited to this task. pcb design guidelines the lands on the chip scale package (cp-48-1) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
adf9010 rev. 0 | page 25 of 28 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 29. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option adf9010bcpz 1 ? 40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 adf9010bcpz-rl 1 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ADF9010BCPZ-RL7 1 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 eval-adf9010ebz1 evaluation board 1 z = rohs compliant part.
adf9010 rev. 0 | page 26 of 28 notes
adf9010 rev. 0 | page 27 of 28 notes
adf9010 rev. 0 | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07373-0-8/08(0)

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